NXP Semiconductors /MIMXRT1021 /IOMUXC /SW_MUX_CTL_PAD_GPIO_AD_B0_06

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_AD_B0_06

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

MUX_MODE=ALT0, SION=DISABLED

Description

SW_MUX_CTL_PAD_GPIO_AD_B0_06 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: PIT_TRIGGER00 of instance: pit

1 (ALT1): Select mux mode: ALT1 mux port: MQS_RIGHT of instance: mqs

2 (ALT2): Select mux mode: ALT2 mux port: LPUART1_TX of instance: lpuart1

3 (ALT3): Select mux mode: ALT3 mux port: QTIMER2_TIMER2 of instance: qtimer2

4 (ALT4): Select mux mode: ALT4 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2

5 (ALT5): Select mux mode: ALT5 mux port: GPIO1_IO06 of instance: gpio1

6 (ALT6): Select mux mode: ALT6 mux port: REF_32K_OUT of instance: anatop

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_AD_B0_06

Links

() ()